1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which includes a test circuit for testing whether or not the wiring lines of the semiconductor integrated circuit work normally.
2. Description of the Related Art
Before an integrated circuit is shipped from a factory, it must be guaranteed that the integrated circuit does not have any defects. In order to confirm that the integrated circuit has no defects, it is necessary to check the integrated circuit by means of a test apparatus.
An integrated circuit is fabricated to attain a certain function, and the test apparatus tests whether or not the fabricated integrated circuit can attain it. The integrated circuit is shipped after the test shows that the integrated circuit does not have any problem.
Integrated circuits developed in recent years are very large in scale, and the functions which have to be attained by use of a single chip are very complex. Since the integrated circuits have to be tested in a large number of points to confirm their functions, testing requires a very long time, resulting in a delay in the shipment of the integrated circuits. In addition, a great expense is required for the test.
In order to make testing easy and quick, an integrated circuit recently developed incorporates not only circuit elements for attaining the required functions, but also test circuits for testing the functions of the integrated circuit. Although a variety of test circuits are provided in accordance with these purposes, a test circuit used for checking the wiring lines of a microcomputer will be briefly described by way of an example.
A comparatively long wiring line, which is generally referred to as a data bus, is incorporated in a semiconductor chip constituting a microcomputer. The circuit elements of the microcomputer exchange data through the data bus.
FIG. 8 shows a conventional microcomputer and depicts one data bus 12. Referring to FIG. 8, circuit blocks 1-9, each made up of various circuits, are arranged on a semiconductor chip 13. Each of the circuit blocks (C.B.) 1-9 is connected to the data bus 12 by way of an input buffer 10 and an output buffer 11. To check whether or not the data bus 12 has an electrical disconnection, the conventional art transfers data from circuit block 1 connected at one end of the data bus 12 toward circuit block 7 connected at the other end of the data bus 12. Then, the conventional art compares the data transmitted from circuit block 1 with the data received by circuit block 7. When these two data are identical to each other, it is determined that the data bus 12 does not have any electrical disconnection.
In the conventional art, however, a complex operation is required for checking the data bus 12. To be more specific, the data bus 12 is checked by the following procedures: setting the data in circuit block 1; transferring the data from circuit block 1 toward circuit block 7; and comparing the data received by circuit block 7 with the data set in circuit block 1. Since these testing procedures are complex, the conventional art inevitably requires a long test time.
FIG. 9 shows another example of a conventional test circuit. In FIG. 9, the same reference numbers as used in FIG. 8 denote structural elements corresponding to those shown in FIG. 8. Referring to FIG. 9, a first test circuit 21 is connected to one end of a data bus 12, and a second test circuit 22 is connected to the other end of the data bus 12. The first and second test circuits do not perform any particular operation when the semiconductor chip 13 is in a normal operation mode. In a test mode, however, the first test circuit 21 has a function of supplying a current to the second test circuit 22 by way of the data bus 12. The second test circuit 22 incorporates a sense amplifier (not shown) used for detecting a current supplied from the first test circuit 21. If the data bus 12 has an electrical disconnection, no current flows from the first test circuit 21 to the second test circuit 22. It is therefore possible to easily check whether or not the data bus 12 has an electrical disconnection. With this circuit configuration, an electrical disconnection of a wiring line can be easily checked, with no need to provide the circuit blocks 1 and 7 mentioned above.
However, in the circuit configuration mentioned above, the first and second test circuits 21 and 22 are connected to the respective ends of one wiring line. Therefore, the integration density of the semiconductor chip is adversely affected. In addition, since a large number of signals are required for controlling the test circuits, the testing method is inevitably complex.
A method for performing the above current conduction test in a simpler way is disclosed in U.S. Pat. No. 4,857,774. According to this U.S. Patent, a large number of wiring lines are connected in series and are checked at one time to detect whether they have an electrical disconnection.
FIG. 10 is a schematic diagram of the circuit disclosed in U.S. Pat. No. 4,857,774. Referring to FIG. 10, a first test circuit 21 is connected to one end of a data bus 12 by way of a wiring line 30 and a switch 31, and a second test circuit 22 is connected to the other end of the data bus 12. In this case, not only the data bus 12, but also the wiring line 30 is checked. The switch 31 is kept OFF in the normal operation mode of the semiconductor chip 13, and is turned on in a test mode in which an electrical disconnection is detected. In the test mode, therefore, the wiring line 30 and the data bus 12 are electrically connected together and can be regarded as constituting a single signal line. In this state, a current is supplied from the first test circuit 21 toward the second test circuit 22 by way of the wiring line 30, the switch 31, and the data bus 12. When the current supplied from the first test circuit 21 is sensed by the second test circuit 22, it is determined that neither the wiring line 30 nor the data bus 12 has an electrical disconnection. Conversely, when the current supplied from the first test circuit 21 is not sensed by the second test circuit 22, it is determined that at least one of the wiring line 30 and data bus 12 has an electrical disconnection.
A large number of wiring lines can be checked at one time in a similar manner. To be specific, switches are provided between the adjacent ones of the wiring lines, and these switches are turned on only when a test is made. This configuration contributes to a reduction in the number of test circuits required, and does not adversely affect the density of integration.
However, the conventional art shown in FIG. 10 will have a problem if the two wiring lines to be connected together by means of a switch are located away from each other. For example, a pattern wherein column-direction wiring lines 42 extend between two row-direction wiring lines 40 and 41, as shown in FIG. 11, is very general in the art. In the pattern shown in FIG. 11, wiring lines 40 and 41 are connected together by means of a single N-channel MOS transistor 43 (a switching element) which is located below wiring lines 42. The transistor 43 is controlled by a gate control signal TEST. In the test mode, the logical level of the gate control signal TEST is set to be "1", and the transistor 43 is turned on in response to this gate control signal. As a result, the wiring lines 40 and 41 are connected together. In the normal operation mode, the logical level of the gate control signal TEST is set to be "0", and the transistor 43 is turned off in response to this gate control signal. As a result, the wiring lines 40 and 41 are electrically disconnected from each other.
FIG. 12A shows a pattern layout corresponding to FIG. 11. As is shown in FIG. 12A, the source of the transistor 43 mentioned above is connected to wiring line 40, and the drain thereof is connected to wiring line 41. Since this transistor is kept off in the normal operation mode, it follows that large capacitors Cp made up of the source or drain are connected to the wiring lines 40 and 41, as shown in FIG. 12B. The capacitance of the capacitors Cp increases with an increase in the distance between the wiring lines 40 and 41. In the normal operation mode, therefore, the signal transmission speed of the wiring lines is greatly lowered by the transistor 43. It should be noted that the test circuits are totally unnecessary in the normal operation mode. Although they are provided for the purpose of simplifying the testing procedures, they undesirably affect the characteristics of the integrated circuit after the test is made.